MEMs-based frequency synthesizers frequently utilize techniques to provide temperature compensation, which can counteract temperature-induced variations in resonant frequency of MEMs resonators. As will be understood by those skilled in the art, MEMs resonators may be used as substitutes for piezoelectric crystal resonators and may be more highly integrated with electrical circuitry (e.g., transimpedance amplifiers) using conventional semiconductor fabrication techniques. Examples of conventional MEMs-based frequency synthesizers with temperature compensation are disclosed in U.S. Pat. Nos. 7,449,968 and 7,755,441 to Cioffi et al., entitled “Frequency and Temperature Compensation Synthesis for a MEMs Resonator.” Among other things, FIG. 3 of the '968 and '441 patents to Cioffi et al. discloses the use of a temperature sensor to provide an indication of the operating temperature of a MEMs resonator, which is provided to an analog-to-digital (ADC) converter. A conventional ADC converter may utilize an analog delta-sigma (ΔΣ) modulator to produce an oversampled output stream of 1-bit digital samples, which can be provided to a digital decimation filter. A digital decimation filter can be used to remove out-of-band quantization noise and unwanted out-of-band signals in the analog input of the modulator. Additional examples of conventional MEMs-based frequency synthesizers with temperature compensation are disclosed in U.S. Pat. Nos. 7,446,619, 7,532,081, 7,443,258 and 7,545,228.
FIGS. 1A-1B illustrate conventional MEMs-based frequency synthesizers 100 that utilize temperature compensation when generating periodic output signals from phase-locked loop (PLL) integrated circuits, which are responsive to periodic input signals derived from MEMs resonators. As shown by FIG. 1A, a MEMs-based frequency synthesizer 100 may include a microelectromechanical resonator circuit 102 containing a trans-impedance amplifier (TIA), which produces a periodic input signal (FIN). This periodic input signal FIN is provided to a phase-locked loop (PLL) integrated circuit 104, which operates as a frequency synthesizer to generate a periodic output signal (Four). As will be understood by those skilled in the art, the frequency of the periodic output signal FOUT is typically much higher than the frequency of the periodic input signal FIN, by virtue of the inclusion of a voltage-controlled oscillator (VCO) (not shown) within the forward signal path of the PLL integrated circuit 104. A fractional-N feedback divider 110 is also provided to generate a feedback reference signal (relative to FIN). This feedback divider 110 is controlled by the magnitude of a feedback divider number (N), which is generated by a summation device 114. As illustrated, this summation device 114 receives, as operands, a programmable divider number (N1) stored within a register 112 and a divider number adjustment (N2) generated by an analog-to-digital converter (ADC) 108, which performs digital filtering and scaling. This ADC 108 is responsive to a clock signal CLK and an analog temperature sensor output signal TS, which is generated by a temperature sensor 106 that is operably coupled to the MEMs resonator 102. Unfortunately, as illustrated by FIG. 1B, the MEMs-based frequency synthesizer 100 of FIG. 1A may be susceptible to a delayed locking phenomenon caused by the faster locking rate of the phase-locked loop integrated circuit 104 (e.g., <10 ms) relative to the ADC converter 108 (e.g., >100 ms). This delayed settling of the ADC converter 108 in response to a reset or start-up event may result in a relatively large adjustment in the divider number (N2), which may cause the PLL integrated circuit 104 to undergo a disruptive unlock/relock transition and modify the frequency of the periodic output signal (FOUT). Thus, notwithstanding the advantages of providing temperature compensation in MEMs-based frequency synthesizers, there continues to be a need to provide enhanced temperature compensation that does not adversely affect PLL locking characteristics.